Training Detail

The Chip Seal Best Practices course assists in the development and implementation of pavement preservation programs by identifying the benefits of using chip seal as part of a preventive maintenance program.

This course has six modules:

1. Introduction into Chip Seals;
2. Designing Chip Seal Mixes;
3. Selecting the Proper Materials for the Chip Seal Mix;
4. Use of Equipment;
5. Proper Construction Practices; and
6. Performance Measures of Chip Seals.

The combination of this information provides an excellent overview of successful chip seal practices worldwide.

This course offers professional development hours (PDHs). You will see the PDHs on your course completion certificate, which also serves as documentation of your attendance. PDH requirements vary, therefore, it is up to you to determine whether or not this particular course qualifies under your State or board requirements.

Training level: Intermediate

Target audience: This training would benefit entry level construction inspectors, maintenance employees, and contractor personnel. It also serves as a refresher training for those already well-versed in the selection and application of chip seal as a preventive maintenance treatment.

Learning outcomes: Upon completion of the course, participants will be able to:

• Define chip seal;
• Describe how chip seals are used as a preventive maintenance treatment for pavement;
• Identify materials used in chip seals;
• Describe the characteristics of chip seal design;
• Identify types of chip seal;
• Identify the important considerations of aggregate and binder selection;
• Describe aggregate-binder compatibility;
• Describe equipment used in chip seal practices;
• Identify important variables in construction practice;
• Define the measures of control implemented over the quality of materials and construction;
• Identify construction best practices;
• Describe the components of engineering-based performance measures;
• Identify qualitative performance indicators for chip seal; and
• Define common visible chip seal distresses.